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nexflash technologies, inc. 1 nxpf001f-0600 06/22/00 ? this document contains preliminary data. nexflash reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 1998, nexflash technologies, inc.. nx29f010 1m-bit (128k x 8-bit) cmos, 5.0v only ultra-fast sectored flash memory features ? ultra-fast performance ? 35, 45, 55, 70, and 90 ns max. access times temperature ranges ? commercial 0 o c-70 o c ? industrial -40 o c-85 o c single 5v-only power supply ? 5v 10% for read, program, and erase cmos low power consumption ? 20 ma (typical) active read current ? 30 ma (typical) program/erase current compatible with jedec-standard pinouts ? 32-pin dip, plcc, tsop program/function compatible with am29f010 ? no system firmware changes ? uses same prom programer algorithm flexible sector architecture ? erase any of eight uniform sectors or full chip erase ? sector protection/unprotection using prom programming equipment 100,000 program/erase cycles embedded algorithms ? automatically programs and verifies data at specified address ? auto-programs and erases the chip or any designated sector data/polling and toggle bits ? detect program or erase cycle completion june 2000 description the nexflash nx29f010 is a 1 megabit (131,072 bytes) single 5.0v-only sectored flash memory. the nx29f010 provides in-system programming with the standard system 5.0v-only vcc supply and can be programmed or erased in standard prom programmers. the nx29f010 offers access times of 35, 45, 55, 70, and 90 ns allowing high-speed controller and dsps' to operate without wait states. byte-wide data appears on dq0-dq7. separate chip enable ( ce ), write enable ( we ), and output enable ( oe ) controls eliminates bus contention. power consumption is greatly reduced when the system places the device into the standby mode. the device is offered in 32-pin plcc, tsop, and pdip packages. principles of operation only a single 5.0v power supply is required for both read and write functions. program or erase operations do not require 12.0v v pp . internally generated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec single power supply flash standard. commands are written to the command register using standard micro- processor write timings. register contents serve as input to an internal state machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. executing the program command sequence invokes the embedded program algorithm, an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.
nx29f010 2 nexflash technologies, inc. nxpf001f-0600 06/22/00 ? we state control command register ce oe pgm voltage generator chip enable/ output enable logic erase voltage generator input/output buffers data latch stb stb y-decoder x-decoder address latch y-gating cell matrix vcc detector timer vcc gnd a0-a16 dq7-dq0 8 8 8 8 8 8 figure 1. nx29f010 block diagram executing the erase command sequence invokes the embedded erase algorithm, an internal algorithm that automatically pre-programs the array to all zeros (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin during erase. by reading the dq7 ( data polling) and dq6 (toggle) status bits, the host system can detect whether a program or erase operation is complete. after completion, the device is ready to read array data or accept another command. the sector erase architecture is designed to allow memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is erased before it is shipped to customers. the hardware data protection includes a low vcc detector that automatically inhibits write operations during power transitions. the hardware sector protection feature will disable both program and erase operations in any combina- tion of the sectors of memory, and is implemented using standard eprom programming algorithm. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunneling. data are programmed one byte at a time using the eprom program- ming algorithm of hot electron injection.
nx29f010 nexflash technologies, inc. 3 nxpf001f-0600 06/22/00 ? table 1. pin descriptions a0-a16 address inputs dq0-dq7 data inputs/outputs ce chip enable input oe output enable input we write enable input vcc power supply voltage gnd ground nc no internal connection dq1 dq2 gnd dq3 dq4 dq5 dq6 a12 a15 a16 nc vcc we nc a14 a13 a8 a9 a11 oe a10 ce dq7 a7 a6 a5 a4 a3 a2 a1 a0 dq0 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 index 4321323130 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 nc we vcc nc a16 a15 a12 a7 a6 a5 a4 oe a10 ce dq7 dq6 dq5 dq4 dq3 gnd dq2 dq1 dq0 a0 a1 a2 a3 figure 3. nx29f010 32-pin plcc figure 4. nx29f010 32-pin tsop figure 2. nx29f010 32-pin plastic dip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd vcc we nc a14 a13 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 pin configurations
nx29f010 4 nexflash technologies, inc. nxpf001f-0600 06/22/00 ? bus operations table 2. device bus operations (1, 2) operation ce ce ce ce ce oe oe oe oe oe we we we we we address (a16-a0) dq0-dq7 read l l h a in data out write l h l a in data in standby v cc 0.5v x x x high-z output disable l h h x high-z notes: 1. l = v il , h = v ih , x = don't care, ain = address in. 2. the sector protect and sector unprotect functions must be implemented via programming equipment. see the sector protection/unprotection section. requirements for reading array data upon device power-up, or after a hardware reset, the internal state machine is set for reading array data. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. the system must drive the ce and oe pins to v il to read array data from the outputs. ce is the power control and selects the device. oe is the output control that passes array data to the output pins. during a read operation, we must remain at v ih . write commands/command sequences the system must drive we and ce to v il , and oe to v ih to write a command or command sequence (which includes programming data to the device and erasing sectors of memory). an erase operation can erase one sector, multiple sectors, or the entire device. the sector address table (see table 3) indicate the address space that each sector occupies. a "sector address" consists of the address bits required to uniquely select a sector. see the "command definitions" section for details on erasing a sector or the entire chip. table 3. sector addresses table sector a16 a15 a14 address range sector a0 0 0 0 00000h-03fffh sector a1 0 0 1 04000h-07fffh sector a2 0 1 0 08000h-0bfffh sector a3 0 1 1 0c000h-0ffffh sector a4 1 0 0 10000h-13fffh sector a5 1 0 1 14000h-17fffh sector a6 1 1 0 18000h-1bfffh sector a7 1 1 1 1c000h-1ffffh after the system writes the auto-select command sequence, the device enters the auto-select mode. the system can then read auto-select codes from the internal register (which is separate from the memory array) on dq7-dq0. standard read cycle timings apply in this mode. refer to the "auto-select mode and auto-select command sequence" sections for more information. program and erase operation status by reading the status bits on dq7-dq0, the system may check the status of the operation during an erase or program operation.
nx29f010 nexflash technologies, inc. 5 nxpf001f-0600 06/22/00 ? table 4. auto-select codes (high voltage method) description ce ce ce ce ce oe oe oe oe oe we we we we we a16-a14 a13-a10 a9 a8-a2 a1 a0 dq7-dq0 manufacturer l l h x x v id x l l 01 (hex) equivalent id device l l h x x v id x l h 20 (hex) equivalent id sector protection l l h sa x v id x h l 01h verification (protected) 00h (unprotected) note: 1. l = v il , h = v ih , v id = 11.5 to 12.5v , sa = a ddress s ector , x = don't care. standby mode in the standby mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe input. the system can place the device in the standby mode when it is not reading or writing to the device. the device enters the cmos standby mode when the ce pin is held at v cc 0.5v. the device enters the ttl standby mode when ce is held at v ih . the device requires the standard access time ( t ce ) before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. output disable mode when the oe = v ih , the output from the device is disabled and the output pins are placed in the high-impedance state. auto-select mode the auto-select mode provides access to the manufacturer and device equivalent codes, as well as sector protection verification codes, via the dq7-dq0 pins. t his mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the auto-select codes can also be accessed in-system through the command register. when using programming equipment, the auto-select mode requires v id (11.5v to 12.5v) on address pin a9. address pins a1 and a0 must be as shown in auto-select codes (high voltage method), table 4. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. refer to the corre- sponding sector address table (table 3). the command definitions table shows the remaining address bits that are don't care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq7-dq0. to access the auto-select codes in-system, the host system can issue the auto-select command via the command register, as shown in the command definitions table. this method does not require v id . see "command definitions" for details on using the auto-select mode. sector protection/unprotection the hardware sector protection feature disables both pro- gram and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. sector protection/unprotection procedure requires a high voltage (v id ) on address pin a9 and the control pins. details on this method are provided in a supplement. contact an nexflash representative to obtain a copy of the appropriate document. the device is shipped with all sectors unprotected. nexflash offers the option of programming and protecting sectors at its factory prior to shipping the device. contact a nexflash representative for details. it is possible to determine whether a sector is protected or unprotected. see "auto-select mode" for details.
nx29f010 6 nexflash technologies, inc. nxpf001f-0600 06/22/00 ? hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the command definitions table). in addition, the following hardware data protection mea- sures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. write pulse "glitch" protection noise pulses of less than 5 ns (typical) on oe , ce , or we do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle, ce and we must be a logical zero while oe is a logical one. power-up write inhibit if we = ce = v il and oe = v ih during power-up, the device does not accept commands on the rising edge of we . the internal state machine is automatically reset to reading array data on power-up. command definitions writing specific address and data commands or sequences into the command register initiates device operations. the command definitions table 5 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we or ce , whichever happens later. all data is latched on the rising edge of we or ce , whichever happens first. refer to the appropriate timing diagrams in the "ac characteristics" section. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. the system must issue the reset command to re-enable the device for reading array data if the error status bit, dq5, is set high after an erase or program operation, or while in the auto-select mode. see the "reset command" section, next. see also "requirements for reading array data" in the "device bus operations" section for more information. the read operation's table provides the read parameters, and read operation timings diagram shows the timing diagram. reset command the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device for reading array data. once erasure begins, however, the device ignores reset com- mands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before program- ming begins. this resets the device to reading array data. once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an auto-select command sequence. once in the auto-select mode, the reset command must be written to return to reading array data. if the error status bit, dq5, goes high during a program or erase operation, writing the reset command returns the device to reading array data. auto-select command sequence the auto-select command sequence allows the host sys- tem to access the manufacturer and device equivalent codes, and determines whether or not a sector is protected. the command definitions table 5 shows the address and data requirements. this method is an alternative to that shown in the auto-select codes (high voltage method) table 4, which is intended for prom programmers and requires v id on address bit a9. the auto-select command sequence is initiated by writing two unlock cycles, followed by the auto-select command. the device then enters the auto-select mode, and the system may read at any address any number of times, without initiating another command sequence.
nx29f010 nexflash technologies, inc. 7 nxpf001f-0600 06/22/00 ? table 5. command definitions bus cycles (2) (hexadecimal) command (1) 1st 2nd 3rd 4th 5th 6th sequence cycles addr data addr data addr data addr data addr data addr data read (3,4) 1rard reset (5) 1 xxxx f0 auto-select (6) manufacturer equiv. id 4 5555 aa 2aaa 55 5555 90 xx00 01 device equiv. id 4 5555 aa 2aaa 55 5555 90 xx01 20 sector protect 4 5555 aa 2aaa 55 5555 90 (sa) 00 verify (7,8) x02 01 program (9) 4 5555 aa 2aaa 55 5555 a0 pa pd chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 sector erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa 30 notes: 1. bus operations are described in table 2. 2. all command bus cycles are write operations, except when reading array or auto-select data. 3. no unlock or command cycles are required when reading array data. 4. ra = address of the memory location to be read; rd = data read from location ra during read operation 5. the reset command is required to return to reading array data when device is in the auto-select mode, or if dq5 goes high (while the device is providing status data). 6. the fourth cycle of the "auto-select command sequence" is a read operation. 7. the data is 00h for an unprotected sector and 01h for a protected sector. see "auto-select command sequence" for more information. 8. sa = address of the sector to be verified (in auto-select mode) or erased. address bits a16-a14 uniquely select any sector 9. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we or ce pulse, whichever happens later; pd = data to be programmed at location pa. data latches on the rising edge of we or ce pulse, whichever happens first. 10. address bit a16 and a15 =x (don't care) for all address commands except for program address (pa), read address (ra) and sector address (sa). 11. x = don't care. a read cycle at address xx00h or retrieves the manufac- turer code. a read cycle at address xx01h returns the device code. a read cycle containing a sector address (sa) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. refer to the sector address tables for valid sector addresses. the system must write the reset command to exit the auto-select mode and return to reading array data. byte program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program setup command. the pro- gram address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automati- cally provides internally generated program pulses and verify the programmed cell margin. the command definitions table (table 5) shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using dq7 or dq6. see "write operation status" for information on these status bits.
nx29f010 8 nexflash technologies, inc. nxpf001f-0600 06/22/00 ? commands written to the device while the embedded program algorithm is in progress are ignored. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a '0' back to a '1'. attempting to do so may halt the operation and set the error status bit, dq5, to '1', or cause the data polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still '0'. only erase operations can convert a '0' to a '1'. note: see command definitions (table 5) for program command sequence. chip erase command sequence chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a setup command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the command definitions table shows the address and data requirements for the chip erase command sequence. commands written to the chip while the embedded erase algorithm is in progress are ignored. the system can determine the status of the erase operation by using dq7 or dq6. see "write operation status" for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 6 illustrates the algorithm for the erase operation. see the erase/program operations tables in "ac charac- teristics" for parameters, and to the chip/sector erase operation timings for timing waveforms. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a setup command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table (table 5) shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. start write program command sequence data poll from system no no yes yes embedded program algorithm in progress verify data? programming complete increment address last address? figure 5. program operation
nx29f010 nexflash technologies, inc. 9 nxpf001f-0600 06/22/00 ? after the command sequence is written, a sector erase time-out of 50 s begins. during the time-out period, addi- tional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command during the time-out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see the "dq3: sector erase timer" section.) the time-out begins from the rising edge of the final we pulse in the command sequence. once the sector erase operation has begun, all other commands are ignored. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7 or dq6. refer to "write operation status" for information on these status bits. figure 6 illustrates the algorithm for the erase operation. refer to the erase/program operations tables in the "ac characteristics" section for parameters, and to the sector erase operations timing diagram for timing waveforms. start write erase command sequence data poll from system embedded erase algorithm in progress data = ffh? no yes erasure complete figure 6. erase operation notes: 1. for erase command sequence. see command definitions table. 2. see "dq3: sector erase timer" for more information.
nx29f010 10 nexflash technologies, inc. nxpf001f-0600 06/22/00 ? write operation status the device provides several bits to determine the status of a write operation: dq3, dq5, dq6, and dq7. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. table 6 and the following subsections describe the functions of these bits. dq7: data data data data data polling the data polling bit, dq7, indicates to the host system whether an embedded algorithm is in progress or com- pleted. data polling is valid after the rising edge of the final we pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum programmed to dq7. when the embedded program algorithm is com- plete, the device outputs the true datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data polling on dq7 is active for approximately 2 s, then the device returns to reading array data. during the embedded erase algorithm, data polling pro- duces a "0" on dq7. when the embedded erase algorithm is complete, data polling produces a "1" on dq7. this is analogous to the complement/true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0". the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on dq7 is active for approximately 100 s, then the device returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq7-dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0-dq6 while output enable ( oe ) is asserted low. the data polling timings (during embedded algorithms) figure in the "ac characteristics" section illustrates this. start read dq7-dq0 addr = va no no yes yes yes dq5 = 1? read dq7-dq0 addr = va fail pass no dq7 = data? dq7 = data? notes: 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 ="1" because dq7 may change simultaneously with dq5. figure 7. data data data data data polling algorithm table 6 shows the outputs for data polling on dq7. figure 7 shows the data polling algorithm.
nx29f010 nexflash technologies, inc. 11 nxpf001f-0600 06/22/00 ? dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete. toggle bit i may be read at any address, and is valid after the rising edge of the final we pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause dq6 to toggle. (the system may use either oe or ce to control the read cycles.) when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approxi- mately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the selected sectors that are protected. if a program address falls within a protected sector, dq6 toggles for approximately 2 s after the program command sequence is written, then returns to reading array data. the write operation status table shows the outputs for toggle bit i on dq6. refer to figure 8 for the toggle bit algorithm, and to the toggle bit timings figure in the "ac characteristics" section for the timing diagram. reading toggle bit dq6 refer to figure 8 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7-dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7-dq0 on the following read cycle. notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to '1'. see text. 3. va = valid address. figure 8. toggle bit algorithm old_dq6 < dq6 addr = va read dq7-dq0 new_dq6 < dq6 start addr = va read dq7-dq0 (1) no no yes yes yes dq5 = 1? old_dq6 < dq6 addr = va read dq7-dq0 new_dq6 < dq6 fail no new_dq6 = old_dq6? new_dq6 = old_dq6? pass
nx29f010 12 nexflash technologies, inc. nxpf001f-0600 06/22/00 ? however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation suc- cessfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially deter- mines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alterna- tively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 8). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a "1." this is a failure condition that indicates the program or erase cycle as not success- fully completed. the dq5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0." only an erase operation can change a "0" back to a "1." under this condition, the device halts the operation, and when the operation has exceeded the timing limits, dq5 produces a "1." under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the sys- tem may read dq3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out is complete, dq3 switches from "0" to "1." the system may ignore dq3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 s. see also the "sector erase command sequence" section. after the sector erase command sequence is written, the system should read the status on dq7 ( data polling) or dq6 (toggle bit i) to ensure the device has accepted the command sequence, and then read dq3. if dq3 is "1", the internally controlled erase cycle has begun; all further commands are ignored until the erase operation is com- plete. if dq3 is "0", the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 6 shows the outputs for dq3. table 6. write operation status operation dq7 (1) dq6 dq5 (2) dq3 embedded dq7# toggle 0 n/a program algorithm embedded 0 toggle 0 1 erase algorithm notes: 1. dq7 requires a valid address when reading status information. 2. dq5 switches to '1' when an embedded program or embedded erase operation has exceeded the maximum timing limits. see "dq5: exceeded timing limits" for more information.
nx29f010 nexflash technologies, inc. 13 nxpf001f-0600 06/22/00 ? absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd any pin except a9 ? 2.0 to +7.0 (2) v a9 ? 2.0 to +12.5 (2) v v cc ? 2.0 to +7.0 (2) v i sc output short circuit current (max. limit) 200 ma t a commercial operating temperature 0 to +70 c t a industrial operating temperature ? 40 to +85 c t stg storage temperature ? 65 to +125 c notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. minimum dc inputs, i/o, and a9 pins voltage is ? 0.5v. during transitions, inputs may undershoot to ? 2.0v for periods less than 20 ns. maximum dc voltage on output pins is vcc + 0.5v, which may overshoot to vcc + 2.0v for periods less than 20 ns. maximum dc voltage on a9 is +12.5v that may overshoot to +12.5v for periods less than 20 ns. 3. no more than one output shorted at one time. duration of short shall not exceed one second. operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial (1) ? 40 c to +85 c 5v 10% note: 1. operating ranges define those limits between which the functionally of the device is guaranteed. capacitance symbol parameter conditions typ. max. unit c in input capacitance v in = 0v 3 6 pf c oc / c output and control capacitance v out = 0v 7 12 pf ? 0.5v +0.8v ? 2.0v 20 ns 20 ns 20 ns vcc + 0.5v vcc + 2.0v +2.0v 20 ns 20 ns 20 ns figure 9. maximum negative overshoot waveform figure 10. maximum positive overshoot waveform
nx29f010 14 nexflash technologies, inc. nxpf001f-0600 06/22/00 ? dc characteristics: ttl/nmos compatible symbol parameter description test conditions min. max. unit i li input leakage current v cc = v cc max., v in = v cc to gnd ? 1.0 a i li 2 a9 input current v cc = v cc max., a9 = 12.5v ? 50 a i lo output leakage current v cc = v cc max., v out = gnd to v cc ? 1.0 a i ccs v cc standby current v cc = v cc max., ce and oe = v ih ? 1.0 ma i cc 1 v cc active current (1) v cc = v cc max., ce = v il , oe = v ih ? 30 ma i cc 2 v cc active current (2,3) v cc = v cc max., ce = v il , oe = v ih ? 50 ma v il input low voltage ? 0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v id voltage for auto-select and v cc = 5.0v 11.5 12.5 v temporary sector unprotect v ol output low voltage i ol = 12 ma, v cc = v cc min. ? 0.45 v v oh output high voltage i oh = ? 2.5 ma, v cc = v cc min. 2.4 ? v notes: 1. the i cc current listed is typically less than 2 ma/mhz with oe at v ih . 2. i cc active while embedded program or embedded erase algorithm is in progress. 3. not 100% tested. dc characteristics: cmos compatible symbol parameter description test conditions min. max. unit i li input leakage current v cc = v cc max., v in = v cc or gnd ? 1.0 a i li 2 a9 input current v cc = v cc max., a9 = 12.5v ? 50 a i lo output leakage current v cc = v cc max., v out = gnd to v cc ? 1.0 a i ccs v cc standby current v cc = v cc max., ce = vcc 0.5v, ? 100 a oe = v ih i cc 1 v cc active current (1) v cc = v cc max., ce = v il , oe = v ih ? 30 ma i cc 2 v cc active current (2,3) v cc = v cc max., ce = v il , oe = v ih ? 50 ma v il input low voltage ? 0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.5 v v id voltage for auto-select and v cc = 5.0v 11.5 12.5 v temporary sector unprotect v ol output low voltage i ol = 12 ma, v cc = v cc min. ? 0.45 v v oh 1 output high voltage i oh = ? 2.5 ma, v cc = v cc min. 0.85 x v cc ? v v oh 2 output high voltage i oh = ? 100 a, v cc = v cc min. v cc ? 0.4 ? v notes: 1. the i cc current listed is typically less than 2 ma/mhz with oe at v ih . 2. i cc active while embedded program or embedded erase algorithm is in progress. 3. not 100% tested.
nx29f010 nexflash technologies, inc. 15 nxpf001f-0600 06/22/00 ? ac characteristics: read only (over operating range) std. -35 -45 -55 -70 -90 symbol parameter min. max. min. max. min. max. min. max. min. max. unit t rc read cycle time (1) 35 ? 45 ? 55 ? 70 ? 90 ? ns t ce chip enable access time (2) ? 35 ? 45 ? 55 ? 70 ? 90 ns t acc address access time (3) ? 35 ? 45 ? 55 ? 70 ? 90 ns t oe output enable access time ? 25 ? 25 ? 30 ? 30 ? 35 ns t df chip enable to output high z (1,4) ? 10 ? 10 ? 15 ? 20 ? 20 ns t df output enable to output high z (1,4) ? 10 ? 10 ? 15 ? 20 ? 20 ns t oeh output enable hold time (1) read 0 ? 0 ? 0 ? 0 ? 0 ? ns toggle & data polling 10 ? 10 ? 10 ? 10 ? 10 ? t oh output hold from first of 0 ? 0 ? 0 ? 0 ? 0 ? ns address, ce or oe whichever occurs first notes: 1. not 100% tested. 2. oe = v il . 3. ce and oe = v il . 4. output driver disable time. 5. see figure 12 and table 6 for test specifications. figure 11. ac waveform: read only t df high-z high-z t rc address stable address ce oe we outputs output valid t oh t oeh t acc t ce t oe
nx29f010 16 nexflash technologies, inc. nxpf001f-0600 06/22/00 ? ac characteristics: erase and program std. -35 -45 -55 -70 -90 symbol parameter min. max. min. max. min. max. min. max. min. max. unit t wc write cycle time (1) 35 ? 45 ? 45 ? 45 ? 90 ? ns t as address setup time 0 ? 0 ? 0 ? 0 ? 0 ? ns t ah address hold time 30 ? 35 ? 45 ? 45 ? 45 ? ns t ds data setup time 15 ? 20 ? 20 ? 30 ? 45 ? ns t dh data hold time 0 ? 0 ? 0 ? 0 ? 0 ? ns t ghwl read recovery time before write 0 ? 0 ? 0 ? 0 ? 0 ? ns ( oe high to we low) t cs ce setup time 0 ? 0 ? 0 ? 0 ? 0 ? ns t ch ce hold time 0 ? 0 ? 0 ? 0 ? 0 ? ns t wp write pulse width 20 ? 25 ? 30 ? 35 ? 45 ? ns t wph write pulse width high 20 ? 20 ? 20 ? 20 ? 20 ? ns t whwh 1 byte programming operation (2) 20 ? 20 ? 20 ? 20 ? 20 ? s t whwh 2 sector erase operation (2) 1.0 ? 1.0 ? 1.0 ? 1.0 ? 1.0 ? sec t vcs v cc setup time (1) 50 ? 50 ? 1.0 ? 1.0 ? 1.0 ? s note: 1. not 100% tested. test conditions table 6. ac test specifications test conditions 35 ns all others unit output load 1 ttl gate output load capacitance, c l 30 100 pf (including jig capacitance) input rise and fall times 5 20 ns input pulse levels 0 to 3.0 0.45 to 2.4 v input timing measurement 1.5 0.8 v reference levels output timing measurement 1.5 2.0 v reference levels device under test 6.2k ? 2.7k ? vcc = 5.0v c l figure 12. test setup
nx29f010 nexflash technologies, inc. 17 nxpf001f-0600 06/22/00 ? figure 13. ac waveform: program operation t wc 555h program command sequence (last two cycles) read status data (last two cycles) pa pa pa t as t vcs t cs t ds t dh t wp t wph t whwh1 t ghwl t ch t ah address ce oe we data a0h pd d out status vcc t wc 2aah erase command sequence (last two cycles) read status data va va sa (555h for chip erase) t as t vcs t cs t ds t dh t wp t wph t whwh2 t ghwl t ch t ah address ce oe we data 55h 30h complete in progress 10h for chip erase vcc figure 14. ac waveform: erase operation note: 1. pa = program address, pd = program data, dout is the true data at the program address. note: 1. sa = sector address (for sector erase), va = valid address for reading status data (see "write operation status").
nx29f010 18 nexflash technologies, inc. nxpf001f-0600 06/22/00 ? figure 15. ac waveform: note: 1. va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. t rc va va va t acc t ce t oeh t oe t ch t df t oh address ce oe we dq7 complement valid data complement true dq0-dq6 status data valid data status data true figure 16. ac waveform: erase and program operations, alternate ce ce ce ce ce controlled writes note: 1. va = valid address, not required for dq6. illustration shows first two status cycles after command sequence, last status read cycle, and array data read cycle. t rc va va va va t acc t ce t oeh t oe t ch t df t oh address ce oe we dq6 valid status (first read) (second read) (stops toggling) valid data status status
nx29f010 nexflash technologies, inc. 19 nxpf001f-0600 06/22/00 ? ac electrical characteristics std. -35 -45 -55 -70 -90 symbol parameter min. max. min. max. min. max. min. max. min. max. unit t wc write cycle time (1) 35 ? 45 ? 55 ? 70 ? 90 ? ns t as addess setup time 0 ? 0 ? 0 ? 0 ? 0 ? ns t ah address hold time 30 ? 35 ? 45 ? 45 ? 45 ? ns t ds data setup time 20 ? 20 ? 20 ? 30 ? 45 ? ns t dh data hold time 0 ? 0 ? 0 ? 0 ? 0 ? ns t oes output enable setup time (1) 0 ? 0 ? 0 ? 0 ? 0 ? ns t ghwl read recovery time before write 0 ? 0 ? 0 ? 0 ? 0 ? ns t ws write enable setup time 0 ? 0 ? 0 ? 0 ? 0 ? ns t wh write enable hold time 0 ? 0 ? 0 ? 0 ? 0 ? ns t cp chip enable pulse width 20 ? 25 ? 30 ? 35 ? 45 ? ns t cph chip enable pulse width high 20 ? 20 ? 20 ? 20 ? 20 ? ns t whwh 1 byte programming operation (2) 20 ? 20 ? 20 ? 20 ? 20 ? s t whwh 2 sector erase operation (2) 1.0 ? 1.0 ? 1.0 ? 1.0 ? 1.0 ? sec note: 1. not 100% tested. 2. see the "erase and programming performance" section for more information. figure 17. ac waveform: note: 1. pa = program address, pd = program data, sa = sector address, dq7# = complement of data input, d out = array data. 2. figure indicates the last two bus cycles of the command sequence. va t wc 555h for program 2aah for erase pa for program sa for sector erase 555h for chip erase a0h for program 55h for erase pd for program 30h for erase 10h for chip erase data# polling t as t ws t ds t dh t cp t cph t whwh1 or 2 t ghel t wh t ah address we oe ce data d out dq7#
nx29f010 20 nexflash technologies, inc. nxpf001f-0600 06/22/00 ? data retention parameter test conditions min. unit minimum pattern data retention time 150 c 10 years vcc current 125 c 20 years erase and programming performance parameter typ. (1) max. (2) unit comments chip/sector erase time 1.0 15 sec excludes 00h programming prior to erase (4) byte programming time 27 300/1000 s commercial / industrial temperature excludes system level overhead (5) chip programming time (3) 3.5 12.5 sec notes: 1. typical program and erase times assume the following conditions: 25 c, 5.0v vcc, 100,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions for commercial and industrial temperature ranges, vcc = 4.5v (4.75v for ? 35), 100,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. if the maximum byte program time given is exceeded, only then does the device set dq5 = 1. see the section on dq5 for further information. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the four-bus-cycle command sequence for programming. see table 2 for further information on command definitions. 6. the device has a typical erase and program cycle endurance of 1,000,000 cycles. 100,000 cycles are guaran- teed. latchup characteristic parameter min. max. (2) input voltage with respect to gnd on i/o pins ? 1.0v v cc + 1.0v vcc current ? 100 ma +100 ma note: 1. includes all pins except vcc. test conditions: vcc = 5.0v, one pin at a time.
nx29f010 nexflash technologies, inc. 21 nxpf001f-0600 06/22/00 ? a d 1 b n seating plane c a1 e a l e b1 s e1 e 600-mil plastic dip (w) inches symbol min max min max min max ref. std. n283240 a 0.160 0.185 0.165 0.180 0.165 0.200 a1 0.020 0.030 0.010 ? 0.020 0.045 b 0.015 0.020 0.018 0.015 0.022 b1 0.050 0.065 0.050 0.045 0.067 c 0.008 0.012 0.010 0.008 0.015 d 1.420 1.460 1.645 1.655 2.045 2.055 e 0.600 0.620 0.590 0.610 0.600 0.620 e1 0.530 0.555 0.540 0.555 0.530 0.560 e a 0.610 0.660 0.620 0.680 0.600 0.680 e 0.100 bsc 0.100 bsc 0.100 bsc l 0.120 0.150 0.120 0.140 0.120 0.138 s 0.055 0.080 0.065 0.085 0.055 0.085 a0 15 2 8 ?? notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. packaging information 600-mil plastic dip package code: w
nx29f010 22 nexflash technologies, inc. nxpf001f-0600 06/22/00 ? packaging information plastic tsop - 32-pins package code: t (type i) d seating plane b e c 1 n e a1 a s h l plastic tsop (t?type i) millimeters inches symbol min max min max ref. std. no. leads 32 a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.005 b 0.17 0.27 0.007 0.009 c 0.10 0.21 0.004 0.008 d 7.90 8.10 0.308 0.316 e 18.30 18.50 0.714 0.722 h 19.80 20.20 0.772 0.788 e 0.50 bsc 0.020 bsc l 0.50 0.70 0.016 0.024 a0 5 0 5 notes: 1. controlling dimension: millimeters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
nx29f010 nexflash technologies, inc. 23 nxpf001f-0600 06/22/00 ? packaging information plcc (plastic leaded chip carrier) package code: pl plastic leaded chip carrier (pl) millimeters inches symbol min max min max ref. std. no. leads 32 a 3.33 3.56 0.131 0.140 a1 0.50 ? 0.020 ? a2 2.67 2.93 0.105 0.115 a3 1.91 0.81 0.026 0.032 b 0.66 8.10 0.311 0.319 b1 0.33 0.54 0.013 0.021 c 0.20 0.35 0.008 0.014 d 13.89 14.05 0.547 0.553 d1 14.86 15.10 0.585 0.595 d2 ? 7.62 ? 0.400 e 11.35 11.51 0.447 0.453 e1 12.32 12.57 0.485 0.495 e2 ? 7.62 ? 0.300 e 1.27 bsc 0.050 bsc 0 o 10 o 0 o 10 o notes: 1. controlling dimension: millimeters, unless other- wise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusions. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 5. nd and ne represent the number of leads in d and e directions, respectively. 6. d1 and e1 should be measured from the bottom of the package. e1 pin 1 a a2 a3 a1 b1 d e d1 b c seating plane d2 e e2
nx29f010 24 nexflash technologies, inc. nxpf001f-0600 06/22/00 ? ordering information commercial range: 0c to +70c speed (ns) order part no. package 35 nx29f010-35w 600-mil plastic dip nx29f010-45pl plcc ? plastic leaded chip carrier nx29f010-35t tsop (type 1) 45 nx29f010-45w 600-mil plastic dip nx29f010-45pl plcc ? plastic leaded chip carrier nx29f010-45t tsop (type 1) 55 nx29f010-55w 600-mil plastic dip nx29f010-55pl plcc ? plastic leaded chip carrier nx29f010-45t tsop (type 1) 70 nx29f010-70w 600-mil plastic dip nx29f010-70pl plcc ? plastic leaded chip carrier nx29f010-70t tsop (type 1) 90 nx29f010-90w 600-mil plastic dip nx29f010-90pl plcc ? plastic leaded chip carrier nx29f010-90t tsop (type 1) note: contact nexflash marketing for availability of dip packages ordering information industrial range: ?40c to +85c speed (ns) order part no. package 45 nx29f010-45pli plcc ? plastic leaded chip carrier NX29F010-45TI tsop (type 1) 55 nx29f010-55pli plcc ? plastic leaded chip carrier nx29f010-55ti tsop (type 1) 70 nx29f010-70pli plcc ? plastic leaded chip carrier nx29f010-70ti tsop (type 1) 90 nx29f010-90pli plcc ? plastic leaded chip carrier nx29f010-90ti tsop (type 1)
nx29f010 nexflash technologies, inc. 25 nxpf001f-0600 06/22/00 ? preliminary designation the ? preliminary ? designation on an nexflash data sheet indicates that the product is not fully characterized. the specifications are subject to change and are not guaran- teed. nexflash or an authorized sales representative should be consulted for current information before using this product. important notice nexflash reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. nexflash assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein re- flect representative operating parameters, and may vary depending upon a user ? s specific application. while the information in this publication has been carefully checked, nexflash shall not be liable for any damages arising as a result of any error or omission. life support policy nexflash does not recommend the use of any of it's products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure in the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless nexflash receives written assurances, to it ? s satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of nexflash is adequately protected under the circumstances. trademarks: nexflash is a trademark of nexflash technologies, inc . all other marks are the property of their respective owner.

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